Author: (\/)@{-}!
•5:55 AM



Much of System Verilog is intended to be Synthesizable


Author: (\/)@{-}!
•4:59 AM
 Tasks and Functions helps the designer to break up large behavioral designs into smaller pieces. The designer has to abstract the similar pieces in the description and replace them either Functions or tasks. This also improves the readability of the code, and hence easier to debug. 

Functions :

  • Keywords:  function , endfunction 
  • Can be used if the procedure
    • Does not have any timing control constructs ; i.e Must execute in Zero-Time.
    • Returns exactly a single value
    • Has at-least one input argument declaration
       Syntax: 
              function   <range_or_type>   function_name;
                       input_port_declaration (s) ;
                       local_variable_declaration (s) ;
                       statement_or_block
                       function_name = (expression);
              endfunction 
       
       Example : 01: Parity Generator
            module   parity;
                  ....
                  reg [31:0] addr;
                  reg parity;

                 initial  begin
                          …
                 end
                 always @(addr)
                     begin
                         parity =  calc_parity(addr);
                         $display("Parity calculated = %b",     calc_parity(addr) );
                     end
                 function calc_parity;
                        input [31:0] address;
                        begin
                            calc_parity = ^address;
                        end
                 endfunction
            endmodule

      Example : 02: Controllable Shifter
           module shifter;
                `define LEFT_SHIFT      1'b0
                `define RIGHT_SHIFT     1'b1
                  .......
                 reg [31:0] addr, left_addr, right_addr;
                 reg control;

                 initial
                    begin
                          …
                    end
                always @(addr)
                    begin
                       left_addr  = shift (addr, `LEFT_SHIFT);
                       right_addr = shift (addr,`RIGHT_SHIFT);
                    end

                function [31:0]  shift;
                         input [31:0] address;
                         input control;
                         begin
                            shift = (control==`LEFT_SHIFT) ?(address<<1) : (address>>1);
                         end
                endfunction
            endmodule


 Tasks:

  • Keywords: task, endtask 
  • Must be used if the procedure has
    • any timing control constructs ; i.e @( ..) , #delay , wait  e.t.c
    • zero or more than one output arguments
    • no input arguments
      Syntax:
             task task_name ;
                    port_declaration (s);
                    local_variable_declaration (s);
                    statement_or_block;
             endtask
  
      Example : 01: Use of input and output arguments
             module operation;
                   parameter delay = 10;

                   .......
                   reg [15:0] A, B;
                   reg [15:0]  AB_AND, AB_OR, AB_XOR;
 
                   initial
                      $monitor( …);
         
                   initial
                      begin
                          …
                      end

                  always @(A or B)
                     begin
                          bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B);
                     end

              
                  task bitwise_oper;
                       output [15:0]  ab_and, ab_or,  ab_xor;
                        input [15:0] a, b;
                        begin
                            #delay 

                                        ab_and = a & b;
                                        ab_or = a | b;
                                        ab_xor = a ^ b;
                        end
                  endtask
            endmodule


       Example : 02 : Use of module local variables
            module sequence;
               .....

               reg clock;

               initial
                 begin
                     …
                 end

               initial
                  init_sequence;


               always
                  asymmetric_sequence;


               task init_sequence;
                  clock = 1'b0;
               endtask

               task asymmetric_sequence;
                   begin
                      #12 clock = 1'b0;
                      #5  clock = 1'b1;
                      #3  clock = 1'b0;
                      #10 clock = 1'b1;
                  end
               endtask
          endmodule
  

Difference between Tasks and Functions 

  • A function can enable (call) just another function (not task) ; A task can enable other tasks and functions.
  • A function execute in 0 simulation time ; A task can execute in non-zero simulation time.
  • A function no timing control statements allowed ; A task may contain any timing control statements
  • A function must have at-least one input argument ; A task can have arbitrary input, output, or inout
  • A function return only a single value ; A task do not return any value
  • Tasks and Functions are defined in a module 
  • Tasks and Functions are local to the module
  • Tasks and Functions can have local variables (registers, but not nets) and events
  • Tasks and Functions contain only behavioral statements
  • Tasks and Functions do not contain initial or always statements
  • Tasks and Functions are called from initial or always statements or other tasks or functions. 
  • Functions are purely combinational , typically used for conversions and commonly used calculations ; Tasks can be used for common Verilog code.
Author: (\/)@{-}!
•11:43 AM

How to generate coverage in VCS (SNPS) , QUESTA and NC

MODELSIM or QUESTA:

STEP1:  Compile your design files with your selected coverage
              QuestaSim  >  vlog  +cover  <bcst>   -f  design_file_list
               +cover [=s b c e f t x]   Enable code coverage metrics by specifying one or more of the characters:
                             s - Statement
                             b - Branch
                             c - Condition
                             e - Expression
                             f  - Fsm
                             t  - Toggle
                             x - Extended toggle
                           Note:  If no character is specified, sbceft  is the default. 

STEP2:      Simulate with the coverage option
                  QuestaSim > vsim  -coverage file_testbench.v
                  and the    run   -all 
         OR, 
                  You can enable it using GUI Mode also.
                  
                  Go to  Compile  >  Compile Options and select the Coverage tab.Another option is,you have to just right-click on your design file at "Project" and choose "Properties". Now, you can see coverage tab. After running the simulation and you will be able to see the coverage tabs for analysis.
                  
                   If you are running regression and you have to save the coverage report of the first test (UCDB file) and merge to the next UCDB of the next test till the regression finishes.And finally you will be able to the  see total Code Coverage.
                  
                   vsim   -c  -do  "coverage  save -onexit  <TESTSET_CODE_COVER>.ucdb ; run -all;exit"  -coverage  -voptargs="+cover=bcfst"  <otherOptions>  <TOP>
Here we tell vsim  to
    1.  Enable code coverage (-coverage),
    2.  The types of coverage to collect (via
 -voptargs=+cover= bcefst").
    3.  To produce a coverage database file on the exit of simulation  (do "coverage save -onexit coverage.ucdb)
    4.  Continue the step1 and Step2 till the regression ends

STEP3:
            Further if you have multiple coverage databases, you can merge them into a single database by using:
                vcover  merge <ucdbFile1>.ucdb   <ucdbFile2>.ucdb  ...  <ucdbFileN>.ucdb   <ucdbFileResult>.ucdb

         
            The finally you can generate a HTML report:
               vcover report  -html  -htmldir  <dirToOutput>  -verbose  -threshL 50  -threshH 90  <ucdbFileResult>.ucdb


NC SIM
ncverilog  <OTHER_ARGUMENTS> +nccoverage+all +nccov58 +nccovworkdir+cov_work +nclexpragma +nccovtest+<testcase_name> +nccovoverwrite +nccovdut+worklib.dut_top -T test_top.sv

1. For switching coverage ON :  Use +nccovfile+dut_cov.txt  while compiling.    //*********************dut_cov.txt****************//
          select_coverage -all -module top
             .......
          select_functional
          select_fsm

    //************************************************//
Note : During simulation use : covoverwrite  -covtest mycov.cov

2. To view coverage:
         iccr -keywords+detail iccr1.cmd        OR
         iccr -keywords+summary iccr2.cmd   OR
         iccr -keywords+dontmerge iccr3.cmd
       
       //********************* iccr1.cmd **********************//
          merge cov_work/design/test* -output merged_dir
          reset_coverage
          load_test cov_work/design/merged_dir                                                                                                    report_detail -instance -betsafd -cgopt top... > detail.rpt
     
      //********************* iccr2.cmd **********************//
          merge cov_work/design/test* -output merged_dir 
          reset_coverage
          load_test cov_work/design/merged_dir                                                                                                    report_summary -instance -cgopt top... > summary.rpt 

      //********************* iccr3.cmd **********************//
          load_test cov_work/design/*
          report_summary -instance -cgopt top... > summary.rpt


VCS

1.  To generate functional coverage
      % urg -dir simv.vdb

2.  To generate code coverage
     % vcs -cm_pp -cm_dir simv.cm  -cm_name  XXX  -cm_report summary
Author: (\/)@{-}!
•10:31 AM
An interface encapsulate a group of inter-related wires, along with their directions (via mod-ports) , synchronization details (via clocking block) , functions and tasks. The major usage of interface is to simplify the connection between modules. 

But Interface can't be instantiated inside program block, class (or similar non-module entity in System Verilog). But we needed to be driven from verification environment like class. To solve this issue virtual interface concept was introduced in System Verilog.

A virtual interface is just a pointer to a physical interface. i.e. Virtual interface is a data type (that implies it can be instantiated in a class) which hold reference to an interface (that implies the class can drive the interface using the virtual interface). It provides a mechanism for separating abstract models and test programs from the actual signals that make up the design. Another big advantage of virtual interface is that class can dynamically connect to different physical interfaces in run time.
Example :
                       
             interface  ahb_vip_intf ; 
                  
 ................ ;

                   ................ ;             
            endinterface 

         

            class AHB_driver ;
                virtual ahb_vip_intf  intf;
                functional new(input virtual ahb_vip_intf intf);
                        this.intf = intf;
                endfunction
              
               task main() ;
                   intf.sig1 =1;
                   ........ ;
               endtask
          endclass
Author: (\/)@{-}!
•8:04 AM

                                                               Asic Design Flow                                                    

Step 1: Prepare an Requirement Specification
Step 2: Create an Micro-Architecture Document.
Step 3: RTL Design & Development of IP's
Step 4: Functional verification all the IP's/Check whether the RTL is free from Linting Errors/Analyze whether the RTL is Synthesis friendly.
  • Step 4a: Perform Cycle-based verification(Functional) to verify the protocol behaviour of the RTL
  • Step 4b: Perform Property Checking , to verify the RTL implementation and the specification understanding is matching.
Step 5: Prepare the Design Constraints file (clock definitions(frequency/uncertainity/jitter),I/O delay definitions, Output pad load definition, Design False/Multicycle-paths) to perform Synthesis, usually called as an SDC synopsys_constraints, specific to synopsys synthesis Tool (design-compiler)

Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which synthesis needs to be targeted for, which has the functional/timing information available for the standard-cell library and the wire-load models for the wires based on the fanout length of the connectivity), RTL files and the Design Constraint files, So that the Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet the design-constraints requirements. After performing synthesis, as a part of the synthesis flow, need to build scan-chain connectivity based on the DFT(Design for Test) requirement, the synthesis tool (Test-compiler), builds the scan-chain.

Step 7: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT) after synthesis.
  • Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is meeting the power targets.
  • Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the design is meeting the functional requirements.
  • Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that the synthesis Tool has not altered the functionality.( Tool: Formality )
  • Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format) file and synthesized netlist file, to check whether the Design is meeting the timing-requirements.( Tool: PrimeTime)
  • Step 7e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement.
Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog format) and the SDC (constraints file) is passed as input files to the Placement and Routing Tool to perform the back-end Actitivities.

Step 9: The next step is the Floor-planning, which means placing the IP's based on the connectivity,placing the memories, Create the Pad-ring, placing the Pads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper accessibility for Package routing), meeting the SSN requirements(Simultaneous Switching Noise) that when the high-speed bus is switching that it doesn't create any noise related acitivities, creating an optimised floorplan, where the design meets the utilization targets of the chip.
  • Step 9a : Release the floor-planned information to the package team, to perform the package feasibility analysis for the pad-ring .
  • Step 9b: To the placement tool, rows are cut, blockages are created where the tool is prevented from placing the cells, then the physical placement of the cells is performed based on the timing/area requirements.The power-grid is built to meet the power-target's of the Chip .
Step 10: The next step is to perform the Routing., at first the Global routing and Detailed routing, meeting the DRC(Design Rule Check) requirement as per the fabrication requirement.

Step 11: After performing Routing then the routed Verilog netlist, standard-cells LEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values of the chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF file is generated. ( Tool: STARRC )

Step 12: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement and Routing step.
  • Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the design has met the power targets.
  • Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether the design is meeting the functional requirement .
  • Step 12c: Perform Formal-verification between RTL vs routed Netlist to confirm that the place & route Tool has not altered the functionality.
  • Step 12d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlist file, to check whether the Design is meeting the timing-requirements.
  • Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement, Peform the Fault-coverage with the DFT tool and Generate the ATPG test-vectors.
  • Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL)
  • Step 12g: Perform DRC(Design Rule Check) verfication called as Physical-verification, to confirm that the design is meeting the Fabrication requirements.
  • Step 12h: Perform LVS(layout vs Spice) check, a part of the verification which takes a routed netlist converts to spice (call it SPICE-R) and convert the Synthesized netlist(call it SPICE-S) and compare that the two are matching.
  • Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design is meeting the ERC requirement.
  • Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed and proper guarding is there in case if we have both analog and digital portions in our Chip. We have seperate Power and Grounds for both Digital and Analog Portions, to reduce the Substrate-noise.
  • Step 12k: Perform seperate STA(Static Timing Analysis) , to verify that the Signal-integrity of our Chip. To perform this to the STA tool, the routed netlist and SPEF file(parasitics including coupling capacitances values), are fed to the tool. This check is important as the signal-integrity effect can cause cross-talk delay and cross-talk noise effects, and hinder in the functionality/timing aspects of the design.
  • Step 12l: Perform IR Drop analysis, that the Power-grid is so robust enough to with-stand the static and dynamic power-drops with in the design and the IR-drop is with-in the target limits.

Step 13: Once the routed design is verified for the design constraints, then now the next step is chip-finishing activities (like metal-slotting, placing de-coupling caps).

Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files which the fab can understand, GDS file.

Step 15: After the GDS file is released , perform the LAPO check so that the database released to the fab is correct.

Step 16: Perform the Package wire-bonding, which connects the chip to the Package.

                                                          (\/)@{-}!                                                                      
Author: (\/)@{-}!
•12:49 AM

JOURNEY THROUGH DARKNESS
This story is about a boy who is born to a family, where the parents earn for their survival and have no big dreams of making their son an Engineer or a Doctor. One day an elder of the village asked the parents to educate their son so that he can put an end to their struggle. Thus the parents decide to send their son to school. They put their son in the government school of their village. The boy did not have high aims from the day one of becoming anything; school was just a routine thing to him. He wanted to be perfect in blending with others in school. So he imitated what others did. His parents always encouraged to study well, so he used to mug up everything to impress his teachers.
In his 7th class he became the topper in his Mandal. The toppers who scored high in Math’s and Physics were felicitated. So this boy thought that he would only get recognized if he tops in Math’s and Physics. That day he decided that he would take Math’s and physics as his subjects to get a job in a government office. In their village hardly 2 or 3 people have studied till intermediate which is their highest qualification. One day a guy from another village who had studied MCA came to their house. He decided to help this boy by guiding him in Math’s and Physics for a good career. By the time he completed his 9th class he had already learned 10thclass syllabus, and passed his 10th standard with first class, which never happened in their village as people did not get more than 3rd or 2nd class.
This boy had a cousin who liked him since they were kids. She dreamed of seeing him become a collector one day. But because if the lack of a standard education in their school, he had to struggle and study very hard to try to make her dream come true. He was the first person to get above 500 Marks in the Mandal. He also got above 90% in his Intermediate. His parents did not have money to send him to a good college so asked him to join any degree in a government college. He joined the degree college in their village and to earn money to pay his fees he joined a small theatre in the booking counter. One day a sir from APRJC came to see a movie but forgot to take the extra change after paying for his ticket. When he came back to take the money he asked the boy where he was studying his engineering. The boy said that he dint have money to pay his fees for engineering. The sir asked to teach mentally challenged kids in his school in subjects like mental ability and Math’s, the sir would in return pay for his semester fees for engineering. The boy had to face many challenges till his second year of engineering. 
Like in every film there is a villan, there too is a villan in this story too, the girl’s father the boy’s uncle. Her father asked her to get married. But both of them had their dreams and wanted to make them true, so requested the boy’s uncle and tried to convince him at their fullest, but in vain. His uncle got the girl married off to an auto driver. With this all the dreams of the boy got shattered. He started drinking…and everything…started neglecting his studies
When he reached his 4th year B.tech the boy fortunately met his School Principal Mr.Ramnarayana Sir who he considers as his God. The boy stayed with him for 1 year and completed his engineering. He guided the boy with his words “WALK SLOWLY….BUT NEVER WALK BACKWARDS”.
Since there were no placements in his college he joined as JTO, and enrolled for Master’s program with JNTU to become a good VLSI engineer. He worked hard to learn from the industries experts, and his hard work paid off when he got a job in a good MNC.
This story once again proves that hard work and dedication gives a man courage and strength to fulfill his dreams and ambitions.

                                 SAY WHAT You Do .. Do What You Say ...
                                                               Prove It .. Improve It ...... (\/)@{-}! 
Author: (\/)@{-}!
•1:12 AM

Directories:

File and directory paths in UNIX use the forward slash "/" to separate directory names in a path.
Examples:
/             -> "root" directory
/usr          -> directory usr (sub-directory of / "root" directory)
/usr/STRIM100 -> STRIM100 is a subdirectory of /usr

Moving around the file system:

pwd -> Show the "present working directory", or current directory.

cd -> Change current directory to your HOME directory.

cd /usr/STRIM100  -> Change current directory to /usr/STRIM100.

cd INIT -> Change current directory to INIT which is a sub-directory of the current directory.

cd ..  -> Change current directory to the parent directory of the current directory.

cd $STRMWORK  -> Change current directory to the directory defined by the environment variable 'STRMWORK'.

cd ~bob  -> Change the current directory to the user bob's home directory (if you have permission).

Listing directory contents:

ls list a directory
ls -l list a directory in long ( detailed ) format

Example:

$ ls -l
drwxr-xr-x 4 cliff user 1024 Jun 18 09:40 WAITRON_EARNINGS
-rw-r--r-- 1 cliff user 767392 Jun 6 14:28 scanlib.tar.gz
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
| | | | | | | | | | |
| | | | | owner group size date time name
| | | | number of links to file or directory contents
| | | permissions for world
| | permissions for members of group
| permissions for owner of file: r = read, w = write, x = execute -=no permission
type of file: - = normal file, d=directory, l = symbolic link, and others...

ls -a List the current directory including hidden files. Hidden files start with "."

ls -ld * List all the file and directory names in the current directory using long format. Without the "d" option, ls would list the contents of any sub-directory of the current. With the "d" option, ls just lists them like regular files.

Changing file permissions and attributes
chmod 755 file => Changes the permissions of file to be rwx for the owner, and rx for the group and the world. (7 = rwx = 111 binary. 5 = r-x = 101 binary).
chgrp user file => Makes file belong to the group user.
chown cliff file => Makes cliff the owner of file.
chown -R cliff dir => Makes cliff the owner of dir and everything in its directory tree.

You must be the owner of the file/directory or be root before you can do any of these things.

Moving, renaming, and copying files:
cp file1 file2 => copy a file
mv file1 newname => move or rename a file
mv file1 ~/AAA/ => move file1 into sub-directory AAA in your home directory.
rm file1 [file2 ...] => remove or delete a file
rm -r dir1 [dir2...] => recursivly remove a directory and its contents BE CAREFUL!
mkdir dir1 [dir2...] => create directories
mkdir -p dirpath => create the directory dirpath, including all implied directories in the path.
rmdir dir1 [dir2...] => remove an empty directory

Viewing and editing files:
cat filename => Dump a file to the screen in ascii.
more filename => Progressively dump a file to the screen: ENTER = one line down
SPACEBAR = page down q=quit.
less filename => Like more, but you can use Page-Up too. Not on all systems.
vi filename => Edit a file using the vi editor. All UNIX systems will have vi in some form.
emacs filename => Edit a file using the emacs editor. Not all systems will have emacs.
head filename => Show the first few lines of a file.
head -n filename => Show the first n lines of a file.
tail filename => Show the last few lines of a file.
tail -n filename => Show the last n lines of a file.

Shells
The behavior of the command line interface will differ slightly depending on the shell program that is being used. Depending on the shell used, some extra behaviors can be quite nifty.You can find out what shell you are using by the command:
echo $SHELL
Of course you can create a file with a list of shell commands and execute it like a program to perform a task. This is called a shell script. This is in fact the primary purpose of most shells, not the interactive command line behavior.

Environment variables
You can teach your shell to remember things for later using environment variables.
For example under the bash shell:
export CASROOT=/usr/local/CAS3.0 => Defines the variable CASROOT with the value /usr/local/CAS3.0.
export LD_LIBRARY_PATH=$CASROOT/Linux/lib => Defines the variable LD_LIBRARY_PATH with the value of CASROOT with /Linux/lib appended, or /usr/local/CAS3.0/Linux/lib.

By prefixing $ to the variable name, you can evaluate it in any command:
cd $CASROOT => Changes your present working directory to the value of CASROOT

echo $CASROOT => Prints out the value of CASROOT, or /usr/local/CAS3.0
printenv CASROOT => Does the same thing in bash and some other shells.


Interactive History
A feature of bash and tcsh (and sometimes others) you can use the up-arrow keys to access your previous commands, edit them, and re-execute them.

Filename Completion
A feature of bash and tcsh (and possibly others) you can use the TAB key to complete a partially typed filename. For example if you have a file called constantine-monks-and-willy-wonka.txt in your directory and want to edit it you can type 'vi const', hit the TAB key, and the shell will fill in the rest of the name for you (provided the completion is unique).

Bash is the way cool shell.
Bash will even complete the name of commands and environment variables. And if there are multiple completions, if you hit TAB twice bash will show you all the completions. Bash is the default user shell for most Linux systems.

Redirection:
grep string filename > newfile => Redirects the output of the above grep
command to a file 'newfile'.
grep string filename >> existfile => Appends the output of the grep command
to the end of 'existfile'.
The redirection directives, > and >> can be used on the output of most commands to direct their output to a file.

Pipes:
The pipe symbol "|" is used to direct the output of one command to the input of another.
For example:
ls -l | more => This commands takes the output of the long format directory list command
"ls -l" and pipes it through the more command (also known as a filter). In this case a very long list of files can be viewed a page at a time.

du -sc * | sort -n | tail
The command "du -sc" lists the sizes of all files and directories in the current working directory. That is piped through "sort -n" which orders the output from smallest to largest size. Finally, that output is piped through "tail" which displays only the last few (which just happen to be the largest) results.

Command Substitution
You can use the output of one command as an input to another command in another way called command substitution. Command substitution is invoked when by enclosing the substituted command in backwards single quotes.
For example:
cat `find . -name aaa.txt`
which will cat ( dump to the screen ) all the files named aaa.txt that exist in the current directory or in any subdirectory tree.

Searching for strings in files: The grep command
grep string filename => prints all the lines in a file that contain the string

Searching for files : The find command
find search_path -name filename

find . -name aaa.txt => Finds all the files named aaa.txt in the current directory or any subdirectory tree.
find / -name vimrc => Find all the files named 'vimrc' anywhere on the system.
find /usr/local/games -name "*xpilot*" => Find all files whose names contain the string 'xpilot' which exist within the '/usr/local/games' directory tree.

Reading and writing tapes, backups, and archives: The tar command
The tar command stands for "tape archive". It is the "standard" way to read and write archives (collections of files and whole directory trees).Often you will find archives of stuff with names like stuff.tar, or stuff.tar.gz. This is stuff in a tar archive, and stuff in a tar archive which has been compressed using the gzip compression program respectivly.
Chances are that if someone gives you a tape written on a UNIX system, it will be in tar format, and you will use tar (and your tape drive) to read it. Likewise, if you want to write a tape to give to someone else, you should probably use tar as well.
Tar examples:
tar xv => Extracts (x) files from the default tape drive while listing (v = verbose)
the file names to the screen.
tar tv => Lists the files from the default tape device without extracting them.
tar cv file1 file2 => Write files 'file1' and 'file2' to the default tape device.
tar cvf archive.tar file1 [file2...] => Create a tar archive as a file "archive.tar" containing file1,file2...etc.
tar xvf archive.tar => extract from the archive file
tar cvfz archive.tar.gz dname => Create a gzip compressed tar archive containing everything in the directory 'dname'. This does not work with all versions of tar.
tar xvfz archive.tar.gz => Extract a gzip compressed tar archive. Does not work with all versions of tar.
tar cvfI archive.tar.bz2 dname => Create a bz2 compressed tar archive. Does not work with all versions of tar

File compression: compress, gzip, and bzip2
The standard UNIX compression commands are compress and uncompress. Compressed files have a suffix .Z added to their name. For example:
compress part.igs => Creates a compressed file part.igs.Z

uncompress part.igs => Uncompresseis part.igs from the compressed file part.igs.Z.
Note the .Z is not required.

Another common compression utility is gzip (and gunzip). These are the GNU compress and
uncompress utilities. gzip usually gives better compression than standard compress,
but may not be installed on all systems. The suffix for gzipped files is .gz
gzip part.igs => Creates a compressed file part.igs.gz
gunzip part.igs => Extracts the original file from part.igs.gz

The bzip2 utility has (in general) even better compression than gzip, but at the cost of longer
times to compress and uncompress the files. It is not as common a utility as gzip, but is
becoming more generally available.
bzip2 part.igs => Create a compressed Iges file part.igs.bz2
bunzip2 part.igs.bz2 => Uncompress the compressed iges file.

Looking for help: The man and apropos commands
Most of the commands have a manual page which give sometimes useful, often more or less detailed, sometimes cryptic and unfathomable discriptions of their usage. Some say they are called man pages because they are only for real men.
Example:
man ls => Shows the manual page for the ls command You can search through the man pages using apropos
Example:
apropos build Shows a list of all the man pages whose discriptions contain the word "build"
Do a man apropos for detailed help on apropos.

Basics of the vi editor
Opening a file => vi filename
Creating text
Edit modes :: These keys enter editing modes and type in the text of your document.
i => Insert before current cursor position
I => Insert at beginning of current line
a => Insert (append) after current cursor position
A => Append to end of line
r => Replace 1 character
R =>Replace mode
Terminate insertion or overwrite mode

Deletion of text
x => Delete single character
dd => Delete current line and put in buffer
ndd => Delete n lines (n is a number) and put them in buffer
J => Attaches the next line to the end of the current line (deletes carriage return).
Oops
u => Undo last command

cut and paste
yy => Yank current line into buffer
nyy => Yank n lines into buffer
p => Put the contents of the buffer after the current line
P => Put the contents of the buffer before the current line

cursor positioning
ctrl+d => Page down
ctrl+u => Page up
:n => Position cursor at line n
:$ => Position cursor at end of file
ctrl+g => Display current line number
h,j,k,l Left,Down,Up, and Right respectivly. Your arrow keys should also work if
if your keyboard mappings are anywhere near sane.

string substitution
:n1,n2:s/string1/string2/[g] => Substitute string2 for string1 on lines n1 to n2. If g is included (meaning global), all instances of string1 on each line are substituted. If g is not included, only the first instance per matching line is substituted.
^ matches start of line
. matches any single character
$ matches end of line

These and other "special characters" (like the forward slash) can be "escaped" with \
i.e to match the string "/usr/STRIM100/SOFT" say "\/usr\/STRIM100\/SOFT"

Examples:
:1,$:s/dog/cat/g => Substitute 'cat' for 'dog', every instance for the entire file - lines 1 to $ (end of file)

:23,25:/frog/bird/ => Substitute 'bird' for 'frog' on lines 23 through 25. Only the first instance
on each line is substituted.

Saving and quitting and other "ex" commands
These commands are all prefixed by pressing colon (:) and then entered in the lower
left corner of the window. They are called "ex" commands because they are commands
of the ex text editor - the precursor line editor to the screen editor
vi. You cannot enter an "ex" command when you are in an edit mode (typing text onto the screen)
Press to exit from an editing mode.

:w                        Write the current file.
:w new.file            Write the file to the name 'new.file'.
:w! existing.file      Overwrite an existing file with the file currently being edited.
:wq                      Write the file and quit.
:q                         Quit.
:q!                        Quit with no changes.

:e filename             Open the file 'filename' for editing.

:set number         Turns on line numbering
:set nonumber      Turns off line numbering